Explanation: CMOS (Complementary Metal-Oxide-Semiconductor) logic is famous for its very low static power consumption because, in a steady state (either high or low), one of its complementary transistors is always off, blocking current flow. However, power consumption in CMOS circuits increases significantly with operating frequency. This is due to the charging and discharging of parasitic capacitances every time the transistors switch states, and also due to "shoot-through" current when both the P-MOS and N-MOS transistors are momentarily on during transitions. TTL (Transistor-Transistor Logic) circuits, while consuming more static power, do not experience the same proportional increase in power with frequency. Therefore, at higher operating frequencies, the dynamic power dissipation of CMOS can rise to levels comparable to, or even exceeding, the total power consumption of TTL circuits. Let's look at why the other options are incorrect: * **A) CMOS logic requires a supply voltage of 5 volts 20%, whereas TTL logic requires 5 volts 5%.** This is incorrect. TTL typically requires a rigid 5V ±5% supply. CMOS, however, is much more flexible and can operate over a wide range of supply voltages (e.g., 1.8V to 18V, depending on the specific family), not just 5V ±20%. * **B) Unused inputs should be tied high or low as necessary especially in the CMOS family.** While this is a true and critical design rule for CMOS (floating inputs can lead to excessive power consumption and damage), the question asks for a comparison of the families. Option C describes a fundamental comparative characteristic of their power behavior under varying conditions. * **D) When a CMOS input is held low, it sources current into whatever it drives.** This is incorrect. CMOS inputs have extremely high impedance and draw very little leakage current. An input does not "drive" anything; rather, it receives a signal. If an input is held low, it would typically *sink* a tiny leakage current from the driving circuit, not source current into it.