Explanation: The component is a D-type Flip-Flop because its output (Q) latches the data input (D) on a clock edge, holding that state until the next active clock edge. It is "Inverting" because the Q output, when active and clocked, is the logical inverse of the D input. The "3-State" characteristic indicates the presence of an additional control input (often an Output Enable or OE pin) that can place the output in a high-impedance (Hi-Z) state. This allows the component to effectively disconnect from a shared bus when not selected, preventing contention. The truth table (Fig. 8A8, which would display these specific behaviors) would show 'H' (High), 'L' (Low), and 'Z' (High-Impedance) states for the output. Options B, C, and D are incorrect because: * B) "Q-type" is not a standard flip-flop classification, and "Non-Inverting" contradicts the "Inverting" behavior that would be evident in the truth table. * C) A "Shift Register" performs sequential data movement, which is a more complex function than a simple D-type flip-flop, and the terminology "Q-type" is still non-standard. * D) "2-State" implies the output can only be High or Low, lacking the crucial Hi-Z state that defines a 3-state device.