Explanation: In digital logic, an active pull-up refers to an output stage that uses a transistor (or transistors) to actively drive the output high. * **TTL (Transistor-Transistor Logic)** NAND gates typically use a "totem-pole" output stage. This configuration includes a transistor that actively pulls the output voltage high when the gate output is meant to be logic '1'. * **CMOS (Complementary Metal-Oxide-Semiconductor)** NAND gates utilize a PMOS transistor connected between the output and the positive supply rail (VDD). This PMOS transistor actively pulls the output high when the gate output is meant to be logic '1'. Therefore, both TTL and CMOS NAND gates share the characteristic of having an active pull-up in their output stage. **Why other options are incorrect:** * **B) Both have three output states:** Standard TTL and CMOS gates have two output states (high or low). A third, high-impedance state (tri-state) is a specialized feature, not inherent to all NAND gates of either family. * **C) Both have comparable input power sourcing:** CMOS inputs are extremely high impedance and draw very little current, primarily leakage. TTL inputs, on the other hand, draw significant current, especially when low, making them very different in power sourcing characteristics. * **D) Both employ Schmitt diodes for increased speed capabilities:** While some logic gates incorporate Schmitt trigger inputs for noise immunity and hysteresis, it's not a universal feature of all TTL or CMOS NAND gates, nor is their primary purpose to increase speed. Schmitt triggers are about input waveform shaping and stability.